The present invention relates generally to a circuit for biasing a transistor, and, more particularly, to a transistor bias circuit that is capable of operating from a power supply that produces a voltage that is only slightly higher than twice the base-emitter voltage of the transistor that is to be biased.
Modern wireless communications devices, such as cellular telephones, are held to ever-higher performance standards. Transmissions must be clear and undistorted, and the battery in the devices must be small and have a long life. In order to meet these consumer requirements, wireless telephone designers have moved away from using traditional silicon-based bipolar transistors as power amplifiers and toward using more exotic transistors, such as heterojunction bipolar transistors (xe2x80x9cHBTsxe2x80x9d) made of aluminum-gallium-arsenide/gallium-arsenide (xe2x80x9cAlGaAs/GaAsxe2x80x9d) and indium-gallium-phosphide/gallium-arsenide (xe2x80x9cInGaP/GaAsxe2x80x9d). Such HBTs provide outstanding power efficiency and high linearity, thus enabling cellular phones to achieve longer battery life and better signal characteristics for voice and data.
Of course, an HBT, like a bipolar junction transistor (xe2x80x9cBJTxe2x80x9d), requires a direct-current current (xe2x80x9cDCxe2x80x9d) bias signal (comprising both a voltage and a current) to be applied to its input terminal to establish its operating point. (The operating point of a transistor may be defined as the point on the transistor""s characteristic curves at which the transistor will operate in the absence of an input signal. See, e.g., John Markus, Electronics Dictionary 445 (4th ed. 1979). Because changes in the DC bias signal affect the operating point of the HBT (and thus adversely affect the linearity of the amplifier), the DC bias signal must be very stable (preferably within 5% to 15%) and unaffected by variations in temperature or in the power supply voltage. Such a DC bias signal is normally generated by a xe2x80x9cbias circuit.xe2x80x9d
A known bias circuit is shown in FIG. 1. Transistor Q2 is a transistor that is to be biased. The circuit comprises: transistor Q1, which is preferably matched to transistor Q2 and is connected to transistor Q2 in a current-mirror configuration; reference resistor R1; feedback transistor Q3; base resistors R2 and R3, which control the amount of bias current supplied to transistors Q1 and Q2; and pull-down resistor R4.
In this circuit, resistor R1 establishes a reference current ICM (for example, 1 milliampere) that passes through transistor Q1. Because transistors Q1 and Q2 are connected in a current-mirror configuration, the reference current ICM is mirrored in the matching transistor Q2 as current IRF. If transistors Q1 and Q2 are matched, the circuit will be relatively insensitive to fluctuations in temperature, since the temperature characteristics of transistors Q1 and Q2 will be substantially the same.
Feedback through transistor Q3 and resistor R2 stabilizes reference current ICM to compensate for fluctuations in reference voltage VREG, in temperature, or in the parameters of the transistors. For example, if reference voltage VREG increases, the voltage at the base of transistor Q3, and subsequently the voltage at the emitter of transistor Q3, also increases. Consequently, the amount of current flowing into the base of mirrored transistor Q1 correspondingly increases. The collector-emitter voltage of transistor Q1 therefore decreases, pulling down the voltage at the collector of transistor Q1 to a value close to what it had been before reference voltage VREG increased.
Transistors Q2 and Q3 and resistors R1 and R2 thus form a negative feedback loop that provides a stable bias voltage at the emitter of transistor Q3 and an accordingly stable current through resistor R3 into the base of transistor Q2, the transistor to be biased. The effectiveness of the feedback is directly impacted by the amount of gain in the loop. Here, the total loop gain is close to the gain of transistor Q1 and is proportional to the size of resistor R1: the larger the size of resistor R1, the more gain there is in the loop and the smaller the loop error will be.
But a serious problem exists with the bias circuit of FIG. 1. Because transistors Q1 and Q3 are xe2x80x9cstackedxe2x80x9d, the circuit operates well only from a power supply voltage that is substantially higher than twice the base-emitter voltage of the transistors. An example is the case where (1) the transistors in FIG. 1. are InGaP/GaAs or AlGaAs/GaAs HBTs (which require a base-emitter voltage (VBE) of about 1.33 V in order to operate); and (2) the power supply voltage is about 3.0 V, which is two-and-a-quarter times the base-emitter voltage of the transistors. Because the emitters of transistors Q1 and Q2 in this circuit are connected to ground (0 V), the voltage at the base of transistor Q1 and the voltage at the base of transistor Q2 must be at least about 1.33 V in order for them to operate. Since the voltage drop across resistor R2 (and also across RF choke L1 and resistor R3) is neglible, the voltage at the emitter of transistor Q3 must therefore be likewise about 1.33 V.
Similarly, transistor Q3 must have a voltage difference of 1.33 V between its base and its emitter. That is, the base of transistor Q3 must be at a voltage potential that is 1.33 V higher than the voltage potential at its emitter. But since, as described above, the voltage at the emitter of transistor Q3 must be at least 1.33 V in order for transistors Q1 and Q2 to operate, the voltage at the base of transistor Q3 must be at least 2.66 V above ground potential (1.33 V at the emitter of transistor Q3 plus the 1.33 V emitter-base junction voltage of transistor Q3), for transistor Q3 to operate.
Furthermore, in order for the voltage at the base of transistor Q3 to be 2.66 V, the voltage drop across resistor R1 must be about 0.34 V (the supply voltage of 3.0 V minus the necessary voltage at the base of transistor Q3 of 2.66 V=0.34 V). If the desired current ICM is 1 mA, for example, then the resistance of resistor R1 would be about 340 ohms (R=V/I=0.34 V/1 mA=340 ohms).When resistor R1 is 340 ohms, the gain in the feedback loop formed by transistors Q1 and Q3 and resistors R1 and R2xe2x80x94which, as described above, is proportional to the size of resistor R1xe2x80x94is generally sufficient to provide an adequately stable bias voltage and current to transistor Q2.
The feedback in the bias circuit of FIG. 1 becomes quickly ineffective, however, if the power supply voltage is lowered from substantially higher than twice the base-emitter voltage of the transistors in the circuit to a value only slightly higher than two times their base-emitter voltage. An example of such a supply voltage is 2.7 V, where the transistors in the circuit are HBTs having VBE=1.33 V. This supply voltage, 2.7 V, is the power supply voltage that is available in modem cellular telephones. In order for the circuit of FIG. 1 to function from a 2.7 V supply voltage, it becomes necessary to reduce the size of resistor R1. The resistance of resistor R1 for this case may be calculated as follows: the supply voltage of 2.7 V minus the necessary bias voltage of 2.66 V is 0.04 V. If current ICM is desired to be 1 mA, resistor R1 must be 40 ohms (R=0.04 V/1 mA=40 ohms).
Thus, the size of resistor R1 when the power supply voltage is 2.7 V (40 ohms) must be more than eight times smaller than the size of resistor R1 when the power supply voltage is 3.0 V (340 ohms). When resistor R1 is as small as 40 ohms, however, the gain in the feedback loop, which is proportional to the size of resistor R1, also is small, and, as a practical matter, is insufficient to compensate adequately for variations in temperature and power supply voltage. In other words, if the temperature or power supply voltage varies by even a small amount, the DC bias signal produced by the bias circuit will reflect the variation. The performance of the bias circuit of FIG. 1 thus is unacceptable if the supply voltage is 2.7 V.
This problem of biasing an HBT when the available power supply voltage is only 2.7 V is addressed in U.S. Pat. No. 6,043,714. The solution described in this patent is to substitute a bipolarjunction transistor (xe2x80x9cBJTxe2x80x9d) for one of cascaded transistors in the bias circuit. But circuits that include both HBTs and BJTs cannot be fabricated on a single integrated circuit, because a BJT requires a silicon substrate, while an InGaP/GaAs or AlGaAs/GaAs HBT requires a gallium-arsenide substrate.
Accordingly, a bias circuit for InGaP/GaAs or AlGaAs/GaAs HBTs is needed that is capable of operating from a supply voltage of as low as 2.7 V and that can be manufactured on a single integrated circuit.
It is therefore an object of the invention to provide a transistor bias circuit that is (1) capable of operating from a power supply that produces a voltage that is only slightly greater than twice the base-emitter voltage of the transistor to be biased; (2) relatively insensitive to fluctuations in supply voltage, temperature, and transistor parameters; and (3) capable of being manufactured on the same integrated circuit as the transistor to be biased.
In accordance with the invention, a bias circuit is provided that is capable of operating with a power supply voltage that is just above twice the value of the base-emitter voltage of the transistors in the circuit. The bias circuit includes a first transistor connected in a current-mirror configuration with the transistor to be biased (xe2x80x9cthe biased transistorxe2x80x9d) and a feedback circuit. The voltage at the collector of the first transistor is fed back via the feedback circuit to control the voltage at the bases of the first transistor and the biased transistor.
The feedback circuit comprises a non-inverting amplifier connected at its input to the collector of the first transistor and at its output to a second transistor connected in an emitter-follower configuration. This second transistor is connected at its collector to the power supply and at its emitter to the node formed by the bases of the first transistor and the biased transistor. It thus establishes base currents entering the first transistor and the biased transistor. The collector-emitter current passing through the first transistor (which is mirrored in the biased transistor) is thereby maintained at a constant level via negative feedback.
The non-inverting amplifier may comprise two or more transistors in a cascade. The bias circuit stage additionally comprises several current-limiting resistive elements and one or more inductors that serve as RF chokes.
Also described herein is a method of biasing a first transistor having a base, emitter, and collector via a circuit including a second transistor connected in a current-mirror configuration with the first transistor. The method includes the steps of monitoring an electrical characteristic (current or voltage) at the collector of the second transistor, amplifying the monitored characteristic, and feeding back the amplified characteristic to control the second transistor. The step of amplifying may further include the steps of inverting the monitored characteristic and then re-inverting the characteristic, such that a non-inverted characteristic is produced. In addition, the method may comprise the step of level-shifting the monitored characteristic.